1. Field of the Invention
The present invention relates to memory devices and, in particular, to the row pull-down function of row drivers used with rows of memory cell arrays.
2. Description of the Related Art
Computer memory cells are in wide use today. Each memory cell stores a bit of data, i.e. a logic-0 or logic-1, sometimes referred to as low or high, respectively, corresponding to the low voltage state (typically V.sub.ss, e.g. ground=0V)) or the high voltage state (typically V.sub.DD, e.g. 3V). New data may be written into the cell, and stored data may be read from the cell. This is typically done by "enabling" the cell by providing a control signal to a control input terminal, which allows data in the cell to be read out on a second, data terminal (or data provided on the data terminal is written in the cell in a write operation).
An array of memory cells are typically provided in a memory array architecture. In a memory cell array, each row of memory cells is typically used to provide storage of larger, multi-bit units of data such as bytes or words. The memory array provides a number of rows or words to provide multiple word storage.
Memory arrays can be implemented in various forms, including Flash EEPROM, DRAM, ROM, and SRAM. Memory arrays are increasingly used in circuits (ICs) in devices such as cellular telephones, answering machines, cordless phones, and other applications. Memory used in ICs in such applications is sometimes referred to as embedded memory. Such applications often require a large amount of memory with fast cycle times. These applications also require the embedded memory circuits to be as physically small as possible to reduce manufacturing costs.
Address information received from a system processor by memory control logic is used by the row decoder of the memory control logic to generate a row control signal which is used to activate the desired row. To activate memory cells of a given row, the "row voltage" (the voltage of a row line coupled to the row control inputs of the memory cells) is raised from low to high (the row line is charged). To deactivate the memory cells, the row voltage is lowered (the row line is discharged). Activating a memory cell enables it to read (or write) data bits which are provided from or to the data columns of the memory cell array, which are coupled via data lines of a data bus to the processor.
Because of capacitance associated with the row line, the row control signal generated by memory control logic is typically not powerful enough to raise and lower the row voltage in sufficient time. Thus, row drivers are typically used for this purpose. The row driver receives the row control signal and then drives the memory cells with a corresponding row driver signal. For example, when the row control signal goes low (logic-0) to enable or activate the row, the row driver, which acts as an inverter, provides a high (logic-1) row driver signal, which feeds into the row control inputs of several memory cells of the row, to enable a write or read of the memory cell with data provided on the data column lines. The row control signal may carry either an "enable" or "disable" row control signal, i.e. it may switch to low (an "enable" signal) to enable or activate the row, and may switch to high (a "disable" signal) to disable or deactivate the row.
In a continuous row (non-segmented) memory array, a single row signal drives each memory cell of the entire row. A prior art continuous row memory array 100 is illustrated in FIG. 1. In a segmented row memory array architecture, which is often used with long, continuous rows of memory cells, each row is divided into sub-rows or local rows. A prior art segmented row memory array 200 is illustrated in FIG. 2.
For example, FIG. 2 shows each row divided into local rows having two memory cells each. (Typically, each local row would have more than two memory cells, for example 128 memory cells.) In this case, the row control signal is used as a global row control signal which is fed into the input of several local row drivers of the row, one for each of several local rows of the row. Each local row driver provides a local row driver signal to the memory cells of the respective local row. Block enable signals are typically used for each local row as well as corresponding local rows of other rows. Each local row can thus be enabled by a combination of activation of the corresponding global row signal for that row plus the activation of the block enable for that local row. Local rows "above" each other in the array typically share the same block enable signal. Thus, to enable the memory cells of a given local row, both its global row control signal is activated (switched to low), and the block enable signal for the local row is activated (switched to high), which causes the local row driver signal for the local row to switch to high.
The row driver must be able to quickly charge the row line to bring it from low to high at the beginning of a memory cell access cycle, and must be able to quickly discharge the row line to pull it from high to low at the end of the memory cell access cycle so that the column data lines can be precharged for the next read cycle, for example. The row driver must therefore be powerful enough to quickly charge and discharge the row line, so that a fast memory access cycle time can be achieved.
Referring now to FIGS. 3A,B, there are illustrated prior art row driver circuits 310, 350. Transistors illustrated with a bubble on the gate line indicate a pmos or p-channel transistor; nmos or n-channel transistors are illustrated without such a bubble.
Each row driver 310, 350 may be used, for example, for the row drivers in segmented row memory array 200 to drive the two memory cells of a local row with the local row driver signal ROWX. Each row driver 310, 350, receives as an input the global row signal GLOBALROWB (i.e., global row 1 or global row 2 of FIG. 2) and the enable block signal EBKB for the local row. In the nomenclature used in the present application, the letter "B" at the end of a signal term (e.g., EBKB or GLOBALROWB) indicates "bar" or inverse, to indicate that the signal is active when it is in the low state.
In both row drivers 310 and 350, transistor M4 is a block selection transistor, transistor M1 is the pull-up transistor which pulls the ROWX or ROWXTW signal up to high at the beginning of a memory access cycle, and transistor M3 is the n-channel pull-down transistor which pulls the ROWX or ROWXTW down to low at the end of a memory access cycle. In row driver 310, transistor M3 is a non-triple-well CMOS process n-channel transistor. In row driver 350, transistor M3 is a triple-well CMOS process n-channel transistor.
Referring now to FIGS. 4A,B, there are shown cross-sectional views illustrating the terminals (S, G, D, BG), parasitic diode D.sub.3, and substrate of the n-channel pull-down transistor M3 of row drivers 310, 350 of FIGS. 3A,B, respectively. The pull-down transistor M3 of row driver 310 contains a parasitic drain diode D3 between the p-type substrate (and backgate terminal BG) and n-type drain region D of n-channel pull-down transistor M3. The triple-well pull-down transistor M3 of row driver 350 contains a parasitic drain diode D3 between the p-type tub or well (and backgate terminal BG) and n-type drain region D of n-channel pull-down transistor M3.
Referring once more to FIGS. 3A,B, row driver circuit 310 comprises transistors M1, M2, M3, M4, and M5, coupled to signal lines GLOBALROWB, VNEG, EBKB, ERASEB, and ROWX, and to V.sub.DD and ground terminals, as shown. Row driver circuit 310 is for use with a Flash EEPROM memory. N-channel pull-down transistor M3 is situated directly in the p-type substrate of the silicon wafer.
Transistor M5 is used to pull ROWX negative when erasing the memory cell of Flash EEPROM memory arrays. Transistor M5 pulls ROWX negative when ERASEB is set negative. When not erasing, ERASEB is fixed at V.sub.DD, turning off transistor M5. Diode D3 is a parasitic drain diode between the p-type substrate (backgate terminal BG) and n-type drain region D of n-channel pull-down transistor M3. If the drain of pull-down transistor M3 were connected directly to ROWX, the parasitic diode D3 would prevent ROWX from going more than one diode drop negative (e.g., -0.7V or -0.5V) because it would be forward biased when ROWX goes negative; thus, p-channel isolation transistor M2 isolates ROWX from the cathode of parasitic diode D3 when M5 is bringing ROWX negative to erase the Flash EEPROM. Except when erasing, transistor M2 is held in the on state by applying a negative potential (VNEG) to its gate. During erase, VNEG is set at ground to turn off M2.
If a circuit such as row driver 310 were used with a non-flash memory such as SRAM or DRAM, transistors M5 and M2 are not needed; transistor M5 and the ERASEB signal would be eliminated, the VNEG signal would be eliminated and ROWX would be directly coupled to the drain of pull-down transistor M3.
Pull-up is accomplished by use of (inverse) enable block signal EBKB, which is used to determine which local row along a global row is selected. When the selected GLOBALROWB signal falls low and the selected EBKB signal falls, the associated local row will be pulled high; otherwise it will stay at ground. For a continuous, non-segmented memory array such as memory array 100, block selection transistor M4 may be omitted, and the source terminal S of pull-up transistor M1 coupled directly to V.sub.DD.
Row driver circuit 350 uses triple-well process n-channel pull-down transistor M3, as illustrated in FIG. 4B. The row output is thus labeled ROWXTW, where "TW" stands for triple well. N-channel pull-down transistor M3 is situated in its own p-well or tub, which in turn is within an n-well or tub, which is itself situated within the p-type substrate silicon wafer. The advantage of using triple-well n-channel transistors such as M3 in row driver 350 is that its backgate connection BG (the p-well) can be lowered below ground potential, in contrast to a non-triple-well n-channel transistor (M3 of circuit 310) which has a backgate terminal fixed at ground along with the substrate.
Because of the triple-well process used for transistor M3 of row driver 350, the anode of a parasitic diode D3 such as illustrated in circuit 310 is not coupled to ground, and thus isolation transistor M2 is not be needed, even if row driver 350 is used with a Flash EEPROM memory. When used as a Flash EEPROM memory row driver, row driver 350 brings ROWXTW negative when the CONTROL signal is set negative. At other times CONTROL is fixed at ground. In memories other than Flash EEPROM, CONTROL is always set at ground.
As for row driver 310, pull-up is accomplished by use of the enable block signal EBKB. As mentioned previously, for a continuous, non-segmented memory array such as memory array 100, block selection transistor M4 may be omitted, and the source terminal S of pull-up transistor M1 coupled directly to V.sub.DD.
The rate at which a row can be discharged is directly related to the physical size of the pull-down transistors M3. Each row driver 310, 350, therefore, uses a relatively large CMOS n-channel pull-down transistors M3, so that the row driver is powerful enough to quickly lower the row voltage (discharge the row) despite the row capacitance. The use of a large pull-down transistor, however, undesirably increases circuit area and also increase the gate capacitance of the row driver circuit. The row driver is itself driven by circuitry providing the row control signal. Thus, although a larger pull-down transistor M3 helps to discharge the row line more rapidly, the relatively large gate capacitance of the row driver tends to limit cycle time because it slows down how quickly the row control signal can cause the row driver to respond to that signal. If a smaller pull-down transistor M3 is utilized, less area is required and the gate capacitance is decreased, but the row pull-down operation takes longer.